1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas, such as gate electrodes and drain and source regions, are connected to the metallization system of the semiconductor device by means of contact elements formed on the basis of electrochemical deposition techniques.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, many field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain terminal and a source terminal.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, memory devices and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor elements but the electrical performance of the complex wiring network, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the individual circuit elements and of the various stacked metallization layers.
Furthermore, in order to establish a connection of the circuit elements with the metallization layers, an appropriate vertical contact structure is provided, which connects to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and to a respective metal line in the metallization layer. The contact structure may comprise contact elements or contact plugs formed in an interlayer dielectric material that encloses and passivates the circuit elements. Upon shrinking the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required packing density in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level may have to be provided with appropriate critical dimensions in the same order of magnitude. The contact elements may typically represent plugs, trenches and the like which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten in combination with appropriate barrier materials has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, the interlayer dielectric material may be formed first and may be patterned so as to receive contact openings, which may extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. For this purpose, openings of very different depth may have to be formed in the interlayer dielectric material in order to connect to gate electrode structures or any other conductive lines formed above the semiconductor layer, while other contact openings have to be extended down to a semiconductor layer, i.e., any contact areas formed therein. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions may be 100 nm and less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy, while the difference in etch depth may additionally contribute to the overall complexity of the patterning process. After exposing the contact areas, frequently provided in the form of metal silicide regions, a barrier material has to be provided, for instance in the form of a material system including titanium and titanium nitride, wherein the titanium material may provide the required adhesion characteristics, while the titanium nitride material may preserve integrity of the interlayer dielectric material during the subsequent deposition of the tungsten material, which may be accomplished on the basis of sophisticated chemical vapor deposition (CVD) techniques in which a direct contact between silicon dioxide-based materials and the deposition ambient for depositing the tungsten material is to be avoided. Typically, the actual deposition of the tungsten material may be preceded by the deposition of a nucleation layer based on tungsten, which may be accomplished by a dedicated deposition step, after which the actual fill material may be provided. After the deposition of these materials, any excess material is removed by chemical mechanical polishing (CMP), thereby forming the insulated contact elements in the interlayer dielectric material. Although the process sequence for patterning the contact openings and filling these openings with barrier materials and tungsten results in contact elements having a desired contact resistivity for semiconductor devices with critical dimensions of 50 nm, a further reduction of the size of the transistors may result in an increased contact resistivity, which may no longer be compatible with the device requirements. That is, upon further device scaling, the increased contact resistivity, which may result from conventional tungsten-based contact regimes, may represent a limiting factor of the operating speed of the integrated circuits, thereby at least partially offsetting many advantages obtained by the further reduction of the critical dimensions in the device level.
One of the reasons for the inferior contact resistivity in tungsten-based contact technologies is the requirement for barrier materials, possibly in combination with a nucleation layer, which may have an increased resistivity compared to the subsequent tungsten fill material. Since a thickness of the barrier materials and the nucleation layer may not be arbitrarily reduced without jeopardizing the effect of this material system, the amount of less conductive materials relative to the tungsten material may thus increase, thereby over-proportionally contributing to an increased contact resistance. For these reasons, it has been suggested to use other materials or deposition regimes in which the presence of a barrier material of reduced conductivity can be avoided. For example, it has been proposed to use wet chemical deposition techniques, such as the electrochemical deposition in the form of an electroless plating process in order to fill in an appropriate metal material, thereby obtaining a superior fill behavior in order to avoid the creation of any voids or other deposition-related irregularities, which may frequently be observed in complex CVD-based techniques in which a complex material system may have to be deposited within sophisticated contact openings, in particular when these openings may have very different depths. Although the electroless deposition technique may be very advantageous with respect to the gap-filling capability and the selection of an appropriate contact material, thereby providing the possibility of avoiding any barrier materials, it turns out that the selective material growth generates in a non-continuous layer of excess metal, which in turn may result in significant contact failures, as will be described with reference to FIGS. 1a-1c in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 and a semiconductor layer 102. The semiconductor layer 102 may comprise any appropriate semiconductor material, such as silicon, silicon/germanium and the like, as is required for forming therein and thereabove circuit elements 150, for instance in the form of transistors, which, in the example shown in FIG. 1a, are illustrated as planar field effect transistors. It should be appreciated that the substrate 101 and the semiconductor layer 102 may represent a silicon- or semiconductor-on-insulator (SOI) configuration, when a buried insulating material (not shown) is provided between the semiconductor layer 102 and the substrate 101. In other cases, the semiconductor material of the layer 102 may directly connect to a crystalline semiconductor material of the substrate 101, thereby forming a bulk configuration. The semiconductor layer 102 comprises a plurality of semiconductor regions or active regions 102A, 120B, 102C, which may be individually laterally delineated by isolation structures (not shown) or which may represent continuous semiconductor regions, depending on device requirements. The active regions 102A, 102B, 102C are to be understood as semiconductor regions in which appropriate dopant profiles are established as required for the various circuit elements, such as the transistors 150. For example, drain and source regions 151 may be provided with an appropriate vertical and lateral dopant profile in accordance with the required electronic characteristics of the transistors 150. Furthermore, the drain and source regions 151 may have areas of superior conductivity, for instance provided in the form of a metal silicide, such as nickel silicide, indicated by 154, which may at least partially act as a contact area for connecting to contact elements to be formed in a later manufacturing stage. Furthermore, the circuit elements 150, for instance in the form of field effect transistors, may also comprise certain components formed above the semiconductor layer 102, for instance in the form of a gate electrode structure 152, which may control the current flow in the transistors 150 upon applying an appropriate control voltage. The gate electrode structures 152 may have any appropriate configuration, that is, they may comprise appropriate gate dielectric materials, for instance in the form of silicon dioxide, silicon oxynitride, high-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of 10.0 and higher, and the like. Moreover, appropriate electrode material or materials may be provided, for instance in the form of doped semiconductor materials, metal-containing materials, such as a metal silicide, electrode metals and the like.
Moreover, in the manufacturing stage shown in FIG. 1a, a contact level 120 is provided in an intermediate manufacturing stage. The contact level 120 is to be understood as a device level of the semiconductor device 100 which provides for an appropriate isolation and passivation of the circuit elements 150 formed in and above the semiconductor layer 102, while at the same time electrically connecting the circuit elements 150 to a metallization system (not shown) that is to be formed above the contact level 120 and which may comprise metal features provided in a plurality of metallization layers in order to form the complex interconnect structure as required by the circuit layout of the device 100. The contact level 120 comprises one or more appropriate dielectric materials, such as a dielectric layer 121, for instance in the form of a silicon nitride material, a nitrogen-enriched silicon carbide material and the like, in combination with a silicon dioxide layer 122, as these materials represent well-established dielectric materials for the contact level of the semiconductor device 100. Moreover, the contact level 120 is illustrated in the manufacturing stage in which contact openings 123A, 123B are provided so as to extend to the semiconductor layer 102, i.e., to any contact areas formed therein, such as the metal silicide regions 154. It should be appreciated that other contact openings (not shown) may extend to the gate electrode structures 152, while, in other cases, any such contact elements extending to different gate levels within the semiconductor device 100 may be formed prior to or after providing the contact openings 123A, 123B.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following process strategies. The active regions 102A, 102B, 102C may be provided upon forming appropriate isolation structures (not shown), which may be accomplished by using sophisticated lithography, patterning, deposition and planarization techniques in order to form trenches in the semiconductor layer 102 so as to extend down to a desired depth and refilling the trenches with an appropriate dielectric material. Prior to or after forming the isolation structures, dopant species may be introduced into the active regions 102A, 102B, 102C as required for adjusting the basic electronic characteristics of the circuit elements 150. Next, the gate electrode structures 152 are formed by applying any appropriate process strategy, depending on the desired configuration of the gate electrode structures 152. For example, appropriate gate dielectric materials may be formed, followed by the deposition of an electrode material, which may then be patterned on the basis of sophisticated lithography and etch techniques. Thereafter, the drain and source regions 151 may be formed, for instance by ion implantation and the like, and after any anneal processes, the metal silicide regions 154 may be provided by applying well-established silicidation techniques. Depending on the overall process strategy, metal silicide regions may also be formed in the gate electrode structures 152, if required. Next, the dielectric materials 121, 122 may be formed, for instance, by plasma enhanced CVD techniques, sub-atmospheric CVD, high density plasma CVD and the like. If required, a planarization of the material 122 may be performed, for instance by using well established CMP techniques, in which well-established process recipes may be applied for removing a portion of the material 122, for instance a silicon dioxide material, thereby obtaining a substantially planar surface topography of the contact level 120. Next, a lithography process may be applied, for instance on the basis of hard mask materials, if required, in order to provide an etch mask (not shown) which defines the lateral position and size of the contact openings 123A, 123B. Next, a complex etch sequence may be applied so as to etch through the dielectric materials 122, 121, thereby finally exposing a portion of the metal silicide regions 154, which may thus act as contact areas.
As previously discussed, the lateral dimensions of the contact openings 123A, 123B, at least in one dimension, i.e., in the horizontal direction of FIG. 1a, may have to be adapted to the reduced lateral dimensions of the circuit elements 150, which may represent transistors formed on the basis of critical dimensions of 50 nm and less, if, for instance, the length of the gate electrode structures 152 is considered. Thus, the contact openings 123A, 123B also have to be formed on the basis of similar critical dimensions, which may increasingly result in reduced device performance caused by an increased contact resistivity when using well-established process strategies based on tungsten and CVD deposition techniques, as indicated above. Consequently, new materials and deposition strategies for the contact level 120 have been proposed in order to avoid the deposition of complex barrier materials and seed materials, as is typically associated with CVD-based tungsten deposition regimes. Therefore, selective deposition techniques have been developed in which appropriate materials may be directly formed on the contact areas 154, without requiring additional barrier and seed materials on the sidewalls of the contact openings 123A, 123B. For example, electroless plating is an electrochemical deposition technique in which an appropriate electrolyte solution is provided, which comprises a reducing agent in combination with a salt including the desired metal component in addition with other chemical agents. Consequently, the deposition of the metal may be achieved on an appropriate surface, such as the contact area 154, which thus acts as a catalyst material, thereby avoiding the application of an external electrical power and also the application of additional seed materials. Consequently, during the deposition process, the metal material is increasingly growing on the contact areas 154 on the basis of an autocatalytic reaction, wherein, during the further advance of the process, the appropriate reducing agent provides for the deposition of the contact metal on the previously deposited contact metal. Consequently, a superior growth behavior from bottom to top may be accomplished on the basis of the electroless deposition process, thereby avoiding any irregularities, such as voids and seams, which may thus result in superior uniformity of the contact metal. Due to the lack of any additional barrier and seed materials, a superior conductivity of the contact elements may be obtained, even if the specific resistivity of the contact metal may be somewhat higher compared to, for instance, a pure tungsten material. For example, cobalt may be efficiently deposited directly on metal silicide regions, such as the contact areas 154, thereby obtaining contact elements of superior conductivity, even though cobalt has a higher specific resistivity compared to tungsten.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, contact elements 123 are formed in the contact openings 123A, 123B on the basis of an electroless plating process, wherein the selective growth behavior and the requirement for providing a certain degree of overgrowth in view of compensating for process and device non-uniformities, such as contact openings of different depth, different growth rates caused by different local growth conditions, which may be correlated with a different density of contact openings, and the like, may result in a “mushroom” like configuration of the contact elements 123. In other words, the conductive contact metal may extend above the dielectric material of the contact level 120, and may laterally extend along a portion of the contact level, however, without forming a continuous metal layer across the entire surface of the contact level 120. The non-continuous configuration of the excess material of the contact elements 123, however, may significantly influence the further processing of the device 100 when applying well-established CMP techniques for removing any excess metal from the contact level 120.
FIG. 1c schematically illustrates a cross-sectional view of a portion of the semiconductor device 100 when performing a CMP process 103 in order to remove any excess material of the contact elements 123. For convenience, a single contact element 123 is illustrated during the polishing process 103, wherein, due to the “mushroom” like shape of the element 123, significant forces, as indicated by 103F, act on the contact element 123. For example, significantly increased sheer forces may result in corresponding torque forces, which in turn may result in a significant displacement of the contact element 123, as indicated by the dashed line. Consequently, significant contact failures may be created during the CMP process 103, which may result in an unacceptable increase of yield losses. For these reasons, currently great efforts are being made in identifying appropriate process parameters for the CMP process 103, for instance in terms of down force, slurry material and the like, in order to reduce the number of contact failures, which may be caused on the basis of CMP recipes that are typically applied in tungsten deposition regimes, in which a continuous tungsten layer is formed on the contact level 120.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.